1. Field of the Invention
The present invention relates to a BiCMOS (having both bipolar and CMOS) integrated circuit device and a fabrication process thereof. In particular, the invention relates to a BiCMOS device including both a CMOSFET region having an SOI (Silicon on Insulator) structure and a bipolar transistor region having a bulk structure, which device is used for LSI for high-speed optical network systems, or LSI for broadband wireless systems and is suited for high speed operation; and a fabrication process of the device.
2. Description of the Related Art
A BiCMOS device which has both an SOI structure region and a bulk structure region (free of an SOI layer) and has a MOS transistor formed in the SOI structure region and a vertical bipolar transistor in the bulk structure region is described in FIG. 4 on page 1382 of xe2x80x9cIEEE Transaction on Electron Devices, Vol. 41, No. 8, pp 1379 to 1387(1994)xe2x80x9d (which will be hereinafter called xe2x80x9cfirst prior artxe2x80x9d).
This first prior art is characterized in that selective epitaxial growth (SEG) and planarizing polishing are conducted, each twice. By the first selective epitaxial growth and first planarizing polishing, the collector region of the bipolar transistor and i-type bulk substrate region for the SOI structure are formed. An n+type collector region is formed by selective diffusion of high-concentration impurities into this collector region. By the second selective epitaxial growth and second planarizing polishing, then-type collector region of the bipolar transistor and an SOI region are formed. By the formation of p type base region and n type emitter region in this nxe2x88x92type collector region, an npn bipolar transistor is formed, while MOSFET is formed in the SOI region.
In addition, a BICMOS technique using an SOI region is disclosed, for example, in U.S. Pat. No. 5,484,738 (second prior art), Japanese Patent Application Laid-Open No. Hei 6-310665 (third prior art), or Japanese Patent Application Laid-Open No. Hei 7-99259 (fourth prior art), while an IC device using SOI is disclosed, for example, in U.S. Pat. No. 5,399,507; (fifth prior art) or U.S. Pat. No. 4,908,328 (sixth prior art). Among them, in the third, fourth and fifth prior arts, a so called SIMOX (separation by implantation of oxygen) technique of forming an SOI region by oxygen ion implantation inside of a semiconductor substrate is employed.
A schematic longitudinal cross-sectional view of the BiCMOS device which was investigated on trial by the present inventors based on the first prior art is shown in FIG. 7. In this diagram, only an npn type vertical bipolar transistor and an n channel insulated gate type transistor (which will hereinafter be called xe2x80x9cMOS transistorxe2x80x9d) are illustrated and a p channel MOS transistor is omitted. In addition, not closely related portions upon comparison with the invention product are omitted.
In FIG. 7, indicated at reference numeral 1 is a p type Si substrate, 2 an SiO2 layer, 3 a p type SOI layer, 4 an n+ type Si layer, 5 a low-doped n type Si layer, 61,7, each an SiO2 film, 8 an n+ type Si layer, 9 an SiO2 film, 10 an n+ type polycrystalline Si film, 11 an SiO2 film, 12 an n+ type SOI layer, 15 a P+ type polycrystalline Si film, 16,17, each an SiO2 film, 18 a p type Si layer, 181 a P+ type Si layer, 20 an n+ type polycrystalline Si film, 21 an n+ type Si layer, 23 an SiO2 film, 24 a metal plug, and 25 to 29, each a metal film. Indicated at reference numeral 4 is a buried n+ type collector layer for the collector, 5 a low-doped n+ type collector layer, 18 a base layer, and 21 an emitter diffusion layer of a bipolar transistor. Reference numeral 12 indicates source/drain diffusion layers of an MOS transistor. Among the metal electrodes, that indicated at reference numeral 25 serves as a base electrode, 26 an emitter electrode and 27 a collector electrode of the bipolar transistor, and 28 a source electrode and 29 a drain electrode of the MOS transistor.
The buried collector layer 4 of a bipolar transistor is formed at an equal surface level to the bulk substrate (SOI-layer supporting substrate) of an SOI structure. In other words, the upper surface of the buried collector layer 4, that is, the lower portion (which will also be called xe2x80x9clower surfacexe2x80x9d or xe2x80x9cbottom portionxe2x80x9d) of the low-doped collector layer 5 is at a substantially equal level to the lower portion (lower surface or bottom surface) of the buried silicon oxide layer (BOX layer) 2. Here, the boundary between the buried collector layer 4 and the low-doped collector layer 5 is defined as to located at a position having an impurity concentration by about one figure lower than the peak of the impurity concentration of the buried collector layer 4, for example, a position having an impurity concentration of 3xc3x971018 cmxe2x88x923. The height level of the surface of the Si substrate in the bulk structure region (that is, the surfaces of the emitter layer 21 and base lead-out layer 181) is at an equal level to the upper surface of the SOI layer 3 and thus, the whole substrate surface is planarized. In this bulk structure region, the low-doped collector layer 5, base layer 18, base lead-out layer 181 and emitter layer 21 of a bipolar transistor are disposed in the height level between the lower portion (lower surface, bottom surface) of the BOX layer 2 and the upper surface of the SOI layer 3.
FIG. 9 schematically illustrates the positional relationship, in the investigated example illustrated in FIG. 7, among the surface of the SOI layer (its height position is indicated at letter A), the surface of the bulk structure region (B), the lower surface of the BOX layer (C) and the upper surface (D) and lower surface (E) of the low-doped collector layer of the bipolar transistor and the height position A of the surface of the SOI layer is equal to the height position B of the surface of the bulk structure region, while the height position E of the lower surface of the low-doped collector layer is substantially equal to the height position C of the lower surface of the BOX layer. Accordingly, the difference (B-E) between the height position B of the surface of the bulk structure region and the height position E of the lower surface of the low-doped collector layer is substantially equal to the total thickness (A-C) of the SOI layer and BOX layer. In this example, (A-C) is set at 0.5 xcexcm (micrometer) and the depth of the base diffusion layer is set at about 0.1 xcexcm (micrometer), resulting in the thickness (D-E) of the low-doped collector layer of about 0.4 xcexcm (micrometer).
Another process for fabricating the integrated circuit device structure as illustrated in FIG. 7 or FIG. 9 is proposed. Described specifically, this process comprises disposing a BOX layer and an SOI layer over the principal surface of a Si semiconductor substrate in advance (preparing an SOI wafer), partially removing the SOI layer and BOX layer from a region wherein a bipolar transistor is to be formed, forming an n type collector layer over the surface of the bulk Si substrate by ion implantation or heat diffusion, thereby forming a buried collector layer 4, subjecting non-doped or nxe2x88x92type Si single crystals to selective epitaxial growth with the n+ type collector layer as a seed, shaving the surface of the Si single crystals in the-bulk structure region by polishing to make its height equal to the surface height of the SOI layer and then forming base and emitter layers on the surface of the bulk structure region. This process is convenient for mass production because a thin SOI layer is formed in advance so that its thickness or properties can be controlled easily.
In order to attain speed increase and reduction in a power consumption amount of the MOS transistor on the SOI layer, it is desired to form the SOI layer with a markedly thin thickness, to be 0.15 xcexcm (micrometer) or less, more desirably to be about 0.05 xcexcm (micrometer). Such a thin film makes it possible to reduce the capacitance of the depletion layer below the gate electrode. In particular, to operate the MOSFET formed on the SOI layer under fully depleted conditions, the SOI layer is desired to be as thin as 0.05 xcexcm (micrometer) or less.
The above-described SIMOX process is a promising for the formation of this markedly thin SOI layer at a low cost with high precision. As a result of an experiment by the present inventors to make, on trial, an SOI structure by the SIMOX technique, however, it was found that the thinning of the SOI layer is accompanied by the thinning of the BOX layer there below. For example, an attempt to form the SOI layer (Si layer) as thin as 0.15 xcexcm (micrometer) or less tends to lead to the formation of the BOX film (SiO2film) having a thickness of 0.2 xcexcm (micrometer) or less. It was found that in most cases, the total thickness of the (SOI layer+BOX layer), that is, the above described (A-C) in FIG. 9, becomes 0.35 xcexcm (micrometer) or less.
Formation of a BICMOS device having a structure as illustrated in FIG. 7 by decreasing the thickness of the (SOI layer+BOX layer) through the SIMOX technique, therefore inevitably leads to a structure as illustrated in FIG. 8. The positional relationship of A to E in this case is illustrated schematically in FIG. 10. The base diffusion layer 18 has a depth of about 0.1 xcexcm (micrometer) or greater. When the relative positional relationship of the height positions A to E is set equal to that of FIG. 7 or FIG. 9, that is, the thickness [A-C] is set 0.35 xcexcm or less, then the thickness [B-E] is about equal to the thickness [A-C], the thickness (D-E) of the low-doped collector layer 5 becomes 0.25 xcexcm (micrometer) or less. Such a decrease in thickness of the low-doped collector layer 5 brings about an increase in the maximum cut-off frequency (fT) of the transistor but increases its parasitic capacitance. When the low-doped collector layer is thinned even to 0.25 xcexcm (micrometer), it is thought effective to increase an impurity concentration of the low-doped collector layer in the transistor intrinsic region by implantation of impurity ions in order to improve fT further while suppressing an increase in the parasitic capacitance to the minimum. A further decrease in the thickness of the low-doped collector layer is not desired, because it drastically heightens parasitic capacitance but its fT improving effect is small. If the (SOI layer+BOX layer) is reduced further to 0.2 xcexcm (micrometer) and the thickness of the low-doped collector layer is set at 0.1 xcexcm (micrometer) or less, breakdown voltage (BVCE) between the emitter and the collector becomes less than 2 V and the parasitic capacitance between base and collector exceeds 1.5 times of the permissible upper limit.
When a bipolar transistor is formed in the bulk structure region in the SOI structure formed by SIMOX, it therefore becomes difficult to attain good transistor properties in the structure as illustrated in FIG. 8, that is, in the structure wherein the relationship of the height positions A to E is equal to that of FIG. 10.
A second problem occurs when the fundamental structure of FIG. 7 is fabricated using an SOI formed by SIMOX technique. As illustrated in FIG. 7, the insulating film which is in contact with the active area of the bipolar transistor in the surrounding form lies between the height position A of the surface of the SOI layer and the height position C of the surface of the bulk substrate in the SOI structure region and its thickness is almost equal to the total thickness of the (SOI layer and BOX layer). As described above, when the SIMOX technique is employed, the total thickness of the (SOI layer+BOX layer) becomes 0.35 xcexcm (micrometer) or less in most cases, resulting in that the insulating film inevitably has similar thickness as illustrated in FIG. 10. The insulating film at this site is desired to have a thickness of at least 0.4 xcexcm (micrometer). A decrease in the film thickness causes a problem such as an increase in the parasitic capacitance between base and emitter. For example, the parasitic capacitance between the base lead-out electrode 15 which occupies relatively a large area and the n+ collector layer 4 tends to increase, resulting in a deterioration in the high frequency properties of the bipolar transistor.
As can be understood from the above description, it is difficult to integrate, on one semiconductor substrate, an MOSFET constituted in an SOI layer of 0.15 xcexcm (micrometer) or less thick which has been formed by the SIMOX technique and a vertical bipolar transistor having an emitter-collector breakdown voltage (BVCE) of at least 2 V.
An object of the present invention is therefore to provide a BiCMOS (having both bipolar and CMOS) device which has both a MOSFET region of an SOI structure (Silicon on Insulator) and a bipolar transistor region of a bulk structure and is suited for high-speed operation.
Another object of the present invention is to provide a low-cost fabrication process of a BiCMOS device wherein a bipolar transistor is formed in a bulk structure region in an SOI structure formed using SIMOX, which process can overcome the above-described problems.
A further specific object of the present invention is to provide an improved BiCMOS device, which has both a CMOSFET region of an SOI (Silicon on Insulator) structure and a vertical bipolar transistor region of a bulk structure, to be used for an LSI for high-speed optical network systems or LSI for broadband wireless systems and suited for high-speed operation.
The above-described problem occurs because all of nxe2x88x92type low-doped collector, base and emitter are formed in the thickness of (SOI layer+BOX layer) as illustrated in FIGS. 8 and 10. This problem can be overcome by disposing or positioning the height position E of the lower surface of the low-doped collector below the height position C of the lower surface of the BOX layer or disposing or positioning the height position D of the upper surface of the low-doped collector layer at a position exceeding the height position C by 0.25 xcexcm (micrometer) or more. A device structure and fabrication process thereof which can carry out such disposal at a low cost will next be described.
In one aspect of the present invention, there is thus provided a BICOMOS semiconductor integrated circuit device comprising a semiconductor substrate having an insulating layer internally and partially embedded therein and a plurality of semiconductor layers disposed on or over said insulating layer, an n channel insulated gate type transistor and a p channel insulated gate type transistor each formed in said plurality of semiconductor layers, a highly-doped collector layer embedded in a said-insulating-layer-free portion of said semiconductor substrate, and a low-doped collector layer disposed on or in said highly-doped collector layer, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of said insulating layer.
In another aspect of the present invention, there is also provided a BICMOS semiconductor integrated circuit device comprising a semiconductor substrate having an insulating layer internally and partially embedded therein and a plurality of semiconductor layers deposited on said insulating layer, an n channel insulated gate type transistor and a p channel insulated gate-type transistor each formed in said plurality of semiconductor layers, a highly-doped collector layer formed by doping impurities on a said-insulating-layer-free portion of the surface of said semiconductor substrate, a low-doped collector layer deposited over said highly-doped collector layer at a substantially equal level to that of the height of the upper surface of the semiconductor layer and a base layer deposited on the upper surface of the low-doped collector layer.
In a further aspect of the present invention, there is also provided a BICMOS semiconductor integrated circuit device, comprising a semiconductor substrate having an insulating layer internally and partially embedded therein and a plurality of semiconductor layers deposited on said insulating layer, an n channel insulated gate type transistor and a p channel insulated gate type transistor each formed in said plurality of semiconductor layers, a highly-doped collector layer formed by doping impurities on a said-insulating-layer-free portion of the surface of said semiconductor substrate, and a low-doped collector layer deposited on said highly-doped collector layer to have a height level higher than the height level of the upper surface of said semiconductor layer.
In a still further aspect of the present invention, there is also provided a BICMOS semiconductor integrated circuit device comprising a semiconductor substrate having an insulating layer internally and partially embedded therein and a plurality of semiconductor layers deposited on said insulating layer, an n channel insulated gate type transistor and a p channel insulated gate type transistor each formed in said plurality of semiconductor layers, a highly-doped collector layer of a vertical bipolar transistor formed in a said-insulating-layer-free portion of said semiconductor substrate, a low-doped collector layer deposited on said highly-doped collector layer and base and emitter layers each formed at an upper surface portion of said low-doped collector layer, wherein the thickness of said low-doped collector layer between said base layer and said highly-doped collector layer is not less than the total thickness of said insulating layer and said semiconductor layer.
In a still further aspect of the present invention, there is also provided a BICMOS semiconductor integrated circuit device comprising a buried insulating layer partially disposed on a semiconductor region, a plurality of semiconductor layers deposited on said insulating layer and having a thickness not greater than 0.15 xcexcm (micrometer), a plurality of n type and p type insulated gate type transistors formed in said semiconductor layer, and a vertical bipolar transistor which has a highly-doped collector layer formed in a said-insulating-layer free portion of said semiconductor region, a low-doped collector layer disposed above said highly-doped collector layer, and base layer and emitter layer each disposed at the upper surface portion of said low-doped collector layer, and has a collector-emitter breakdown voltage of 2 V or greater.
In a still further aspect of the present invention, there is also provided a process for fabricating a BICMOS semiconductor integrated circuit device, which comprises preparing a semiconductor wafer having an insulating layer embedded in a semiconductor region and a semiconductor layer deposited on said insulating layer, partially removing said semiconductor layer and said insulating layer there below to expose said semiconductor region below said insulating layer, forming a highly-doped collector layer of a vertical bipolar transistor by ion implantation inside of said exposed semiconductor region, forming at least a part of a low-doped collector layer at a site both inside of said semiconductor and on said highly-doped collector layer, and forming a base layer and an emitter layer at the surface portion of said collector layer.
In a high-speed BiCMOS integrated circuit device having, formed thereon, an MOS transistor in the SOI layer of the SOI wafer and a vertical bipolar transistor on the bulk region, it is preferred to adjust the total thickness of the (SOI layer+BOX layer) to 0.35 xcexcm (micrometer) or less and, in particular, the thickness of the SOI layer to 0.15 xcexcm (micrometer) or less in order to increase the speed of the MOS transistor and reduce the consumption amount of power. The present invention makes it possible to maintain the BVCE breakdown voltage of the bipolar transistor at 2 V or greater and suppress the parasitic capacitance between base and collector as small as possible even at such a thin thickness, and moreover to reduce the production cost of the BiCMOS integrated circuit device having such excellent properties.